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English [en], .pdf, 🚀/lgli/lgrs/nexusstc/scihub/zlib, 9.0MB, 📘 Book (non-fiction), nexusstc/Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)/d716461ed524b0ea8b3b9c4e7832cbc0.pdf
Constraining Designs for Synthesis and Timing Analysis [recurso electrónico] A Practical Guide to Synopsys Design Constraints (SDC) 🔍
Springer-Verlag New York, 1st ed. 2013, New York, NY, 2013
Sridhar Gangadharan, Sanjay Churiwala (auth.) 🔍
description
This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints. · Provides a hands-on guide to synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints; · Includes key topics of interest to a synthesis, static timing analysis or place and route engineer; · Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing; · Explains fundamental concepts and provides exact command syntax
Alternative filename
lgrsnf/A:\_for_add\springeruns\10.1007%2F978-1-4614-3269-2.pdf
Alternative filename
lgli/A:\_for_add\springeruns\10.1007%2F978-1-4614-3269-2.pdf
Alternative filename
scihub/10.1007/978-1-4614-3269-2.pdf
Alternative title
Constraining designs for syntheis and timing analysis : a practical guide to synopsis design constraints (SDC)
Alternative author
Gangadharan, Sridhar, Churiwala, Sanjay
Alternative author
Sanjay Churiwala, Sridhar Gangadharan
Alternative publisher
Springer New York : Imprint: Springer
Alternative publisher
Springer London, Limited
Alternative edition
United States, United States of America
Alternative edition
2013, US, 2013
Alternative edition
2013, 2014
Alternative edition
uuuu
metadata comments
sm41109422
metadata comments
{"edition":"1","isbns":["1461432685","1461432693","9781461432685","9781461432692"],"last_page":226,"publisher":"Springer New York"}
Alternative description
Front Matter....Pages i-xxvii
Introduction....Pages 1-8
Synthesis Basics....Pages 9-15
Timing Analysis and Constraints....Pages 17-33
SDC Extensions Through Tcl....Pages 35-46
Clocks....Pages 47-55
Generated Clocks....Pages 57-69
Clock Groups....Pages 71-80
Other Clock Characteristics....Pages 81-94
Port Delays....Pages 95-115
Completing Port Constraints....Pages 117-130
False Paths....Pages 131-144
Multi Cycle Paths....Pages 145-155
Combinational Paths....Pages 157-166
Modal Analysis....Pages 167-175
Managing Your Constraints....Pages 177-192
Miscellaneous SDC Commands....Pages 193-207
XDC: Xilinx Extensions to SDC....Pages 209-218
Back Matter....Pages 219-226
date open sourced
2013-10-20
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